As the size of transistors descends further into the deep submicron range, integrated circuits are becoming increasingly susceptible to operational disturbances caused by fluctuations in the surrounding environment. These fluctuations are often referred to as “soft errors.” It is believed that these soft errors are primarily produced by energetic particle strikes. By imparting unwanted charge into random nodes of an integrated circuit, these particle strikes can either toggle the states of storage elements or cause poorly-timed transient glitches that disrupt the latching of combinational results. In older technologies, this was not a significant problem, because the capacitances of the larger devices and the higher supply voltages were such that they could often absorb all of the energy of a single particle without changing their logic value. However, with ever shrinking geometries and higher-density circuits, the issue of soft errors and reliability in complex System on Chip (SoC) design is set to become an increasingly challenging issue for the industry as a whole.
There are a number of factors that contribute to present trends toward increasing soft-error rates. For example, high energy particles, such as cosmic radiation or alpha particles emanating from packaging materials can interfere with charges held within sensitive nodes in the circuit, thereby affecting the logic state. When these high energy particles strike a sensitive node region, they can cause a bit in the memory cell to change states or flip. These soft errors, which are also known as single-event upsets, generally affect storage elements, such as memory, latches and registers. As silicon process geometries shrink and systems become more complex, particle collision is more likely to impact the stored charge sufficiently enough to change its state. There is also mounting evidence to support the likelihood of more than one error occurring simultaneously, i.e., multi-bit errors.
In fact, it is generally believed that the frequency of system errors due to charged particle strikes is not insignificant. Soft error problems represent a considerable cost and reputation challenge for integrated chip manufacturers. In safety critical applications, for example space, military or medical equipment applications, unpredictable reliability can represent considerable risk, not only in terms of the potential human cost, but also in terms of corporate liability, exposing manufacturers to potential litigation. In commercial consumer applications, there is again significant potential economic impact to consider. For high-volume, low-margin products, high levels of product failure may necessitate the costly management of warranty support or expensive field maintenance. Once again, the effect on brand reputation may be considerable.
The integrated circuit industry has attempted to address this problem in a number of ways. For example, the industry has employed redundant operating systems, but while this solution is effective, it is quite expensive. Another attempted solution has been in the area of circuit design by increasing device capacitance, raising the supply voltage, or adding feedback loops to overcome any transient spikes on the input. The feedback loops in storage elements can be oversized to make them less likely to toggle states. Yet another has been software design to detect and correct the error. Any one of these actions, however, has a direct penalty in area, power, speed, or cost, all of which are less than complete solutions.
Accordingly, what is needed in the art is an improved method for reducing soft error effects without incurring the disadvantages associated with the method discussed above.